@inproceedings{7cd573a78e0149a6b1b1e10a565de48d,
title = "1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance",
abstract = "A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.",
keywords = "Monte-Carlo simulation, STT-MRAM, array, reference, sense amplifier",
author = "Hiroki Koike and Sadahiko Miura and Hiroaki Honjo and Tosinari Watanabe and Hideo Sato and Soshi Sato and Takashi Nasuno and Yasuo Noguchi and Mitsuo Yasuhira and Takaho Tanigawa and Masakazu Muraguchi and Masaaki Niwa and Kenchi Ito and Shoji Ikeda and Hideo Ohno and Tetsuo Endoh",
year = "2015",
month = jul,
day = "2",
doi = "10.1109/IMW.2015.7150264",
language = "English",
series = "2015 IEEE 7th International Memory Workshop, IMW 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 IEEE 7th International Memory Workshop, IMW 2015",
note = "2015 7th IEEE International Memory Workshop, IMW 2015 ; Conference date: 17-05-2015 Through 20-05-2015",
}