We have successfully developed advanced low-damage and short-failure-free RIE technology under 300 mm process down to 32 nmφ MTJ patterning. By using the developed RIE technology, we have achieved significant improvement in TMR ratio, coercivity, thermal stability factor, and the ratio of thermal stability factor to intrinsic critical current compared to those using conventional RIE technology. By using our advanced RIE technology, we also fabricated 1T-1MTJ type embedded 2Mb-STT-MRAM chips with the 61 nmφ-perpendicular-MTJs using the double-MgO free layer under 90 nm CMOS-MTJ hybrid 300 mm process. Advantage of our advanced RIE technology has been demonstrated with their high yield and excellent shmoo plot. The STT-MRAM technology with high-performance MTJ using low-damage RIE patterning process contributes to future high-density embedded STT-MRAM.