1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Research output: Contribution to journalConference article

10 Citations (Scopus)

Abstract

The design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation is presented. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation. The arithmetic circuits show promise as an emerging technology supporting giga-scale integration.

Original languageEnglish
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume38
Publication statusPublished - 1995 Feb 1
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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