15 ps Cryogenic operation of 0.19-μm-LG n+- p+ double-gate SOI CMOS

Toshihiro Sugii; Tetsu Tanaka; Hiroshi Horie; Kunihiro Suzuki

doi:10.1117/12.221150

15 ps Cryogenic operation of 0.19-μm-L_G n⁺- p⁺ double-gate SOI CMOS

Toshihiro Sugii, Tetsu Tanaka, Hiroshi Horie, Kunihiro Suzuki

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

We demonstrated a CMOS invertor with a 15 ps propagation delay (t_pd) at 77 K. This device uses n⁺- p⁺ double-gate SOI MOSFETs with a gate length (L_G) of 0.19 μm and a gate oxide thickness (t_ox) around 9 nm. The channel doping concentration of this device is maintained as low as 10¹⁵ cm^-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to a smaller t_pd than any other reported values for a given L_G. Although the threshold voltage (V_th) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling t_ox and the SOI thicknesses (t_Si).

Original language	English
Pages (from-to)	74-82
Number of pages	9
Journal	Proceedings of SPIE - The International Society for Optical Engineering
Volume	2636
DOIs	https://doi.org/10.1117/12.221150
Publication status	Published - 1995 Dec 1
Externally published	Yes
Event	Microelectronic Device and Multilevel Interconnection Technology - Austin, TX, United States Duration: 1995 Oct 25 → 1995 Oct 26

Keywords

CMOS
Cryo-CMOS
Cryogenic
Deep-submicron
Double-gate
SOI
Threshold voltage

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Computer Science Applications
Applied Mathematics
Electrical and Electronic Engineering

Access to Document

10.1117/12.221150

Cite this

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title = "15 ps Cryogenic operation of 0.19-μm-LG n+- p+ double-gate SOI CMOS",

abstract = "We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+- p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 μm and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to a smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).",

keywords = "CMOS, Cryo-CMOS, Cryogenic, Deep-submicron, Double-gate, SOI, Threshold voltage",

author = "Toshihiro Sugii and Tetsu Tanaka and Hiroshi Horie and Kunihiro Suzuki",

year = "1995",

month = dec,

day = "1",

doi = "10.1117/12.221150",

language = "English",

volume = "2636",

pages = "74--82",

journal = "Proceedings of SPIE - The International Society for Optical Engineering",

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publisher = "SPIE",

note = "Microelectronic Device and Multilevel Interconnection Technology ; Conference date: 25-10-1995 Through 26-10-1995",

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TY - JOUR

T1 - 15 ps Cryogenic operation of 0.19-μm-LG n+- p+ double-gate SOI CMOS

AU - Sugii, Toshihiro

AU - Tanaka, Tetsu

AU - Horie, Hiroshi

AU - Suzuki, Kunihiro

PY - 1995/12/1

Y1 - 1995/12/1

N2 - We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+- p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 μm and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to a smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).

AB - We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+- p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 μm and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to a smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).

KW - CMOS

KW - Cryo-CMOS

KW - Cryogenic

KW - Deep-submicron

KW - Double-gate

KW - SOI

KW - Threshold voltage

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JF - Proceedings of SPIE - The International Society for Optical Engineering

SN - 0277-786X

T2 - Microelectronic Device and Multilevel Interconnection Technology

Y2 - 25 October 1995 through 26 October 1995

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