15 ps Cryogenic operation of 0.19-μm-LG n+- p+ double-gate SOI CMOS

Toshihiro Sugii, Tetsu Tanaka, Hiroshi Horie, Kunihiro Suzuki

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+- p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 μm and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to a smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).

Original languageEnglish
Pages (from-to)74-82
Number of pages9
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume2636
DOIs
Publication statusPublished - 1995 Dec 1
Externally publishedYes
EventMicroelectronic Device and Multilevel Interconnection Technology - Austin, TX, United States
Duration: 1995 Oct 251995 Oct 26

Keywords

  • CMOS
  • Cryo-CMOS
  • Cryogenic
  • Deep-submicron
  • Double-gate
  • SOI
  • Threshold voltage

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '15 ps Cryogenic operation of 0.19-μm-L<sub>G</sub> n<sup>+</sup>- p<sup>+</sup> double-gate SOI CMOS'. Together they form a unique fingerprint.

Cite this