Abstract
We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+- p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 μm and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to a smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).
Original language | English |
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Pages (from-to) | 74-82 |
Number of pages | 9 |
Journal | Proceedings of SPIE - The International Society for Optical Engineering |
Volume | 2636 |
DOIs | |
Publication status | Published - 1995 Dec 1 |
Externally published | Yes |
Event | Microelectronic Device and Multilevel Interconnection Technology - Austin, TX, United States Duration: 1995 Oct 25 → 1995 Oct 26 |
Keywords
- CMOS
- Cryo-CMOS
- Cryogenic
- Deep-submicron
- Double-gate
- SOI
- Threshold voltage
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering