14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

Kyoya Takano; Ryuichi Fujimoto; Mizuki Motoyoshi; Kosuke Katayama; Minoru Fujishima

doi:10.1109/RWS.2013.6486699

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm². It can operate with a data rate of 10Gbps.

Original language	English
Title of host publication	RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013
Pages	235-237
Number of pages	3
DOIs	https://doi.org/10.1109/RWS.2013.6486699
Publication status	Published - 2013 May 1
Externally published	Yes
Event	2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013 - Austin, TX Duration: 2013 Jan 20 → 2013 Jan 23

Other

Other	2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013
City	Austin, TX
Period	13/1/20 → 13/1/23

Keywords

amplifier array
CMOS
DC offset canceller
limiting amplifiers

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Electrical and Electronic Engineering
Communication

Access to Document

10.1109/RWS.2013.6486699

Cite this

Takano, K, Fujimoto, R, Motoyoshi, M, Katayama, K & Fujishima, M 2013, 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. in RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013., 6486699, pp. 235-237, 2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013, Austin, TX, 13/1/20. https://doi.org/10.1109/RWS.2013.6486699

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title = "14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers",

abstract = "A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.",

keywords = "amplifier array, CMOS, DC offset canceller, limiting amplifiers",

author = "Kyoya Takano and Ryuichi Fujimoto and Mizuki Motoyoshi and Kosuke Katayama and Minoru Fujishima",

year = "2013",

month = may,

day = "1",

doi = "10.1109/RWS.2013.6486699",

language = "English",

isbn = "9781467329309",

pages = "235--237",

booktitle = "RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013",

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AU - Takano, Kyoya

AU - Fujimoto, Ryuichi

AU - Motoyoshi, Mizuki

AU - Katayama, Kosuke

AU - Fujishima, Minoru

PY - 2013/5/1

Y1 - 2013/5/1

N2 - A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.

AB - A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.

KW - amplifier array

KW - CMOS

KW - DC offset canceller

KW - limiting amplifiers

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BT - RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013

T2 - 2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013

Y2 - 20 January 2013 through 23 January 2013

ER -

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

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