1.44F2 memory cell technology with the stacked-surrounding gate transistor (S-SGT) DRAM

T. Endoh, H. Sakuraba, K. Shinmei, F. Masuoka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The proposed Stacked-Surrounding Gate Transistor (S-SGT) DRAM is structured by stacking several SGT-type cells in series vertically. When S-SGT DRAM is stacking 4 cells and one bit-line of both S-SGT and normal DRAM has 1K-bit cells, S-SGT DRAM can realize cell area per bit of 1.44F2, while cell area per bit of normal DRAM with the same design rule is 12F2, and S-SGT DRAM achieves 230% larger the signal capacitance over total bit-line capacitance (Cs/Cb) than that of normal DRAM.

Original languageEnglish
Title of host publication2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
PublisherIEEE
Pages451-454
Number of pages4
ISBN (Print)0780352351, 9780780352353
Publication statusPublished - 1999 Jan 1
Event22nd International Conference on Microelectronics (MIEL 2000) - Nis, Yugoslavia
Duration: 2000 May 142000 May 17

Publication series

Name2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
Volume2

Other

Other22nd International Conference on Microelectronics (MIEL 2000)
CityNis, Yugoslavia
Period00/5/1400/5/17

ASJC Scopus subject areas

  • Engineering(all)

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    Endoh, T., Sakuraba, H., Shinmei, K., & Masuoka, F. (1999). 1.44F2 memory cell technology with the stacked-surrounding gate transistor (S-SGT) DRAM. In 2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings (pp. 451-454). (2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings; Vol. 2). IEEE.