1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology

Uroschanit Yodprasit, Kosuke Katayama, Ryuichi Fujimoto, Mizuki Motoyoshi, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.

Original languageEnglish
Title of host publication2013 IEEE International Semiconductor Conference Dresden - Grenoble
Subtitle of host publicationTechnology, Design, Packaging, Simulation and Test, ISCDG 2013
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 - Dresden, Germany
Duration: 2013 Sep 262013 Sep 27

Publication series

Name2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013

Conference

Conference2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013
CountryGermany
CityDresden
Period13/9/2613/9/27

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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