TY - GEN
T1 - 10 nmf perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction with over 400°C high thermal tolerance by boron diffusion control
AU - Honjo, H.
AU - Sato, Hideo
AU - Ikeda, S.
AU - Sato, Soshi
AU - Watanebe, T.
AU - Miura, S.
AU - Nasuno, T.
AU - Noguchi, Y.
AU - Yasuhira, M.
AU - Tanigawa, T.
AU - Koike, H.
AU - Muraguchi, Masakazu
AU - Niwa, Masaaki
AU - Ito, Kenchi
AU - Ohno, H.
AU - Endoh, T.
PY - 2015/8/25
Y1 - 2015/8/25
N2 - We have developed a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) stack with CoFeB free layer and Co/Pt multilayer based synthetic ferrimagnetic (SyF) pinned layer that withstand annealing at a temperature up to 420°C (that compatible with CMOS BEOL process) by controlling boron diffusion. We demonstrated the 10 nmφ p-MTJ with double CoFeB/MgO interface tolerable against 400°C annealing which is a requisite building block for realization of high density spin transfer torque magnetic random access memory (STT-MRAM) in reduced dimensions.
AB - We have developed a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) stack with CoFeB free layer and Co/Pt multilayer based synthetic ferrimagnetic (SyF) pinned layer that withstand annealing at a temperature up to 420°C (that compatible with CMOS BEOL process) by controlling boron diffusion. We demonstrated the 10 nmφ p-MTJ with double CoFeB/MgO interface tolerable against 400°C annealing which is a requisite building block for realization of high density spin transfer torque magnetic random access memory (STT-MRAM) in reduced dimensions.
KW - MRAM
KW - MTJ
UR - http://www.scopus.com/inward/record.url?scp=84950997819&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84950997819&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2015.7223661
DO - 10.1109/VLSIT.2015.7223661
M3 - Conference contribution
AN - SCOPUS:84950997819
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - T160-T161
BT - 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Symposium on VLSI Technology, VLSI Technology 2015
Y2 - 16 June 2015 through 18 June 2015
ER -