0.6μm2 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST)

L. Nesbit, J. Alsmeier, B. Chen, J. DeBrosse, P. Fathey, M. Gall, M. Gambino, J. Gambino, S. Gernhardt, H. Ishiuchi, R. Kleinhenz, J. Mandelman, T. Mii, M. Morilado, A. Nitayama, S. Parke, al et al

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

Abstract

In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd Strap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 μm2 at 0.25 μm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 μm design rules, are presented in this paper.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Editors Anon
PublisherPubl by IEEE
Pages627-630
Number of pages4
ISBN (Print)0780314506
Publication statusPublished - 1993 Dec 1
EventProceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA
Duration: 1993 Dec 51993 Dec 8

Publication series

NameTechnical Digest - International Electron Devices Meeting
ISSN (Print)0163-1918

Other

OtherProceedings of the 1993 IEEE International Electron Devices Meeting
CityWashington, DC, USA
Period93/12/593/12/8

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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