0.6μm2 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST)

L. Nesbit; J. Alsmeier; B. Chen; J. DeBrosse; P. Fathey; M. Gall; M. Gambino; J. Gambino; S. Gernhardt; H. Ishiuchi; R. Kleinhenz; J. Mandelman; T. Mii; M. Morilado; A. Nitayama; S. Parke; al et al

0.6μm² 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST)

L. Nesbit, J. Alsmeier, B. Chen, J. DeBrosse, P. Fathey, M. Gall, M. Gambino, J. Gambino, S. Gernhardt, H. Ishiuchi, R. Kleinhenz, J. Mandelman, T. Mii, M. Morilado, A. Nitayama, S. Parke, al et al

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

34 Citations (Scopus)

Abstract

In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd Strap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 μm² at 0.25 μm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 μm design rules, are presented in this paper.

Original language	English
Title of host publication	Technical Digest - International Electron Devices Meeting
Editors	Anon
Publisher	Publ by IEEE
Pages	627-630
Number of pages	4
ISBN (Print)	0780314506
Publication status	Published - 1993 Dec 1
Event	Proceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA Duration: 1993 Dec 5 → 1993 Dec 8

Publication series

Name	Technical Digest - International Electron Devices Meeting
ISSN (Print)	0163-1918

Other

Other	Proceedings of the 1993 IEEE International Electron Devices Meeting
City	Washington, DC, USA
Period	93/12/5 → 93/12/8

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Fingerprint Dive into the research topics of '0.6μm<sup>2</sup> 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST)'. Together they form a unique fingerprint.

Cite this

Nesbit, L., Alsmeier, J., Chen, B., DeBrosse, J., Fathey, P., Gall, M., Gambino, M., Gambino, J., Gernhardt, S., Ishiuchi, H., Kleinhenz, R., Mandelman, J., Mii, T., Morilado, M., Nitayama, A., Parke, S., & et al, A. (1993). 0.6μm² 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST). In Anon (Ed.), Technical Digest - International Electron Devices Meeting (pp. 627-630). (Technical Digest - International Electron Devices Meeting). Publ by IEEE.

0.6μm² 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST). / Nesbit, L.; Alsmeier, J.; Chen, B.; DeBrosse, J.; Fathey, P.; Gall, M.; Gambino, M.; Gambino, J.; Gernhardt, S.; Ishiuchi, H.; Kleinhenz, R.; Mandelman, J.; Mii, T.; Morilado, M.; Nitayama, A.; Parke, S.; et al, al.

Technical Digest - International Electron Devices Meeting. ed. / Anon. Publ by IEEE, 1993. p. 627-630 (Technical Digest - International Electron Devices Meeting).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nesbit, L, Alsmeier, J, Chen, B, DeBrosse, J, Fathey, P, Gall, M, Gambino, M, Gambino, J, Gernhardt, S, Ishiuchi, H, Kleinhenz, R, Mandelman, J, Mii, T, Morilado, M, Nitayama, A, Parke, S & et al, A 1993, 0.6μm² 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST). in Anon (ed.), Technical Digest - International Electron Devices Meeting. Technical Digest - International Electron Devices Meeting, Publ by IEEE, pp. 627-630, Proceedings of the 1993 IEEE International Electron Devices Meeting, Washington, DC, USA, 93/12/5.

Nesbit, L. ; Alsmeier, J. ; Chen, B. ; DeBrosse, J. ; Fathey, P. ; Gall, M. ; Gambino, M. ; Gambino, J. ; Gernhardt, S. ; Ishiuchi, H. ; Kleinhenz, R. ; Mandelman, J. ; Mii, T. ; Morilado, M. ; Nitayama, A. ; Parke, S. ; et al, al. / 0.6μm² 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST). Technical Digest - International Electron Devices Meeting. editor / Anon. Publ by IEEE, 1993. pp. 627-630 (Technical Digest - International Electron Devices Meeting).

@inproceedings{842c79e0e008446ca52f24743c807bd3,

title = "0.6μm2 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST)",

abstract = "In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd Strap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 μm2 at 0.25 μm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 μm design rules, are presented in this paper.",

author = "L. Nesbit and J. Alsmeier and B. Chen and J. DeBrosse and P. Fathey and M. Gall and M. Gambino and J. Gambino and S. Gernhardt and H. Ishiuchi and R. Kleinhenz and J. Mandelman and T. Mii and M. Morilado and A. Nitayama and S. Parke and {et al}, al",

year = "1993",

month = dec,

day = "1",

language = "English",

isbn = "0780314506",

series = "Technical Digest - International Electron Devices Meeting",

publisher = "Publ by IEEE",

pages = "627--630",

editor = "Anon",

booktitle = "Technical Digest - International Electron Devices Meeting",

note = "Proceedings of the 1993 IEEE International Electron Devices Meeting ; Conference date: 05-12-1993 Through 08-12-1993",

}

TY - GEN

T1 - 0.6μm2 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST)

AU - Nesbit, L.

AU - Alsmeier, J.

AU - Chen, B.

AU - DeBrosse, J.

AU - Fathey, P.

AU - Gall, M.

AU - Gambino, M.

AU - Gambino, J.

AU - Gernhardt, S.

AU - Ishiuchi, H.

AU - Kleinhenz, R.

AU - Mandelman, J.

AU - Mii, T.

AU - Morilado, M.

AU - Nitayama, A.

AU - Parke, S.

AU - et al, al

PY - 1993/12/1

Y1 - 1993/12/1

N2 - In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd Strap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 μm2 at 0.25 μm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 μm design rules, are presented in this paper.

AB - In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd Strap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 μm2 at 0.25 μm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 μm design rules, are presented in this paper.

UR - http://www.scopus.com/inward/record.url?scp=0027814761&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027814761&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027814761

SN - 0780314506

T3 - Technical Digest - International Electron Devices Meeting

SP - 627

EP - 630

BT - Technical Digest - International Electron Devices Meeting

A2 - Anon, null

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE International Electron Devices Meeting

Y2 - 5 December 1993 through 8 December 1993

ER -