This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast but without static noise margin (SNM) and those too slow but with too much SNM are salvaged. Thus, this dynamic PG control greatly improves the variation tolerance of 6-Tr FinFET SRAM. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an Lg-20nm low-standby-power (LSTP) technology.