0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits

S. O'uchi, K. Endo, Y. X. Liu, T. Nakagawa, T. Matsukawa, Y. Ishikawa, J. Tsukada, H. Yamauchi, T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast but without static noise margin (SNM) and those too slow but with too much SNM are salvaged. Thus, this dynamic PG control greatly improves the variation tolerance of 6-Tr FinFET SRAM. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an Lg-20nm low-standby-power (LSTP) technology.

Original languageEnglish
Title of host publicationESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages474-477
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 27
Externally publishedYes
Event36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
Duration: 2010 Sep 142010 Sep 16

Publication series

NameESSCIRC 2010 - 36th European Solid State Circuits Conference

Other

Other36th European Solid State Circuits Conference, ESSCIRC 2010
CountrySpain
CitySevilla
Period10/9/1410/9/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits'. Together they form a unique fingerprint.

Cite this