0. 5 mu M CMOS TECHNOLOGY FOR 5. 6NSEC HIGH SPEED 16 multiplied by 16 BIT MULTIPLIER.

Kazushi Tsuda, Hiroshi Takato, Naoko Takenouchi, Kenji Tsuchiya, Yukihito Oowaki, Kenji Numata, Akihiro Nitayama

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

An advanced half-micrometer CMOS technology using a novel STD (sidewall transistor with double doped brain) PMOSFET structure with reduced parasitic resistance and capacitance is presented. An extremely high-speed and high-reliability CMOS 16 multiplied by 16 bit multiplier has been realized. The multiplication time is 5. 6 ns at 4. 0-V supply voltage, and the power-delay product is 0. 5 pJ/b**3, which is the smallest value ever reported, including bipolar and GaAs multipliers.

Original languageEnglish
Pages (from-to)109-110
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1987 Dec 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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