An advanced half-micrometer CMOS technology using a novel STD (sidewall transistor with double doped brain) PMOSFET structure with reduced parasitic resistance and capacitance is presented. An extremely high-speed and high-reliability CMOS 16 multiplied by 16 bit multiplier has been realized. The multiplication time is 5. 6 ns at 4. 0-V supply voltage, and the power-delay product is 0. 5 pJ/b**3, which is the smallest value ever reported, including bipolar and GaAs multipliers.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 1987 Dec 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering